Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

INDEX
INDEX-2 Vol. 2B
Compatibility, software, 1-4
Condition code flags, EFLAGS register, 3-115
Condition code flags, x87 FPU status word
flags affected by instructions, 3-15
setting, 3-404, 3-406, 3-409
Conditional jump, 3-495
Conforming code segment, 3-514
Constants (floating point), loading, 3-342
Control registers, moving values to and from, 3-597
Cosine, x87 FPU operation, 3-310, 3-379
CPL, 3-109, 4-394
CPUID instruction, 3-160, 3-175
36-bit page size extension, 3-175
APIC on-chip, 3-174
basic CPUID information, 3-161
cache and TLB characteristics, 3-161, 3-177
CLFLUSH flag, 3-175
CLFLUSH instruction cache line size, 3-170
CMPXCHG16B flag, 3-172
CMPXCHG8B flag, 3-174
CPL qualified debug store, 3-172
debug extensions, CR4.DE, 3-174
debug store supported, 3-175
deterministic cache parameters leaf, 3-163
extended function information, 3-165
feature information, 3-173
FPU on-chip, 3-173
FSAVE flag, 3-175
FXRSTOR flag, 3-175
HT technology flag, 3-176
IA-32e mode available, 3-166
input limits for EAX, 3-167
L1 Context ID, 3-172
local APIC physical ID, 3-171
machine check architecture, 3-175
machine check exception, 3-174
memory type range registers, 3-174
MONITOR feature information, 3-180
MONITOR/MWAIT flag, 3-172
MONITOR/MWAIT leaf, 3-164, 3-165
MWAIT feature information, 3-180
page attribute table, 3-175
page size extension, 3-174
performance monitoring features, 3-180
physical address bits, 3-167
physical address extension, 3-174
power management, 3-180
processor brand index, 3-170, 3-180
processor brand string, 3-166, 3-180
processor serial number, 3-162, 3-175
processor type field
, 3-170
PTE global bit, 3-174
RDMSR flag, 3-174
returned in EBX, 3-170
returned in ECX & EDX, 3-171
self snoop, 3-176
SpeedStep technology, 3-172
SS2 extensions flag, 3-175
SSE extensions flag, 3-175
SSE3 extensions flag, 3-172
SSSE3 extensions flag, 3-172
SYSENTER flag, 3-174
SYSEXIT flag, 3-174
thermal management, 3-180
thermal monitor, 3-172, 3-175, 3-176
time stamp counter, 3-174
using CPUID, 3-160
vendor ID string, 3-168
version information, 3-161, 3-180
virtual 8086 Mode flag, 3-173
virtual address bits, 3-167
WRMSR flag, 3-174
CQO instruction, 3-254
CR0 control register, 4-315
CS register, 3-87, 3-466, 3-484, 3-502, 3-592, 4-128
CVTDQ2PD instruction, 3-189
CVTDQ2PS instruction, 3-191
CVTPD2DQ instruction, 3-194
CVTPD2PI instruction, 3-197
CVTPD2PS instruction, 3-200
CVTPI2PD instruction, 3-203
CVTPI2PS instruction, 3-206
CVTPS2DQ instruction, 3-209
CVTPS2PD instruction, 3-212
CVTPS2PI instruction, 3-215
CVTSD2SI instruction, 3-218
CVTSD2SS instruction, 3-221
CVTSI2SD instruction, 3-224
CVTSI2SS instruction, 3-227
CVTSS2SD instruction, 3-230
CVTSS2SI instruction, 3-233
CVTTPD2DQ instruction, 3-239
CVTTPD2PI instruction, 3-236
CVTTPS2DQ instruction, 3-242
CVTTPS2PI instruction, 3-245
CVTTSD2SI instruction, 3-248
CVTTSS2SI instruction, 3-251
CWD instruction, 3-254
CWDE instruction, 3-104
C/C++ compiler intrinsics
compiler functional equivalents, C-1
composite
, C-15
description of, 3-12
lists of, C-1
simple, C-2
D
D (default operation size) flag, segment descriptor,
4-128, 4-134, 4-213
DAA instruction, 3-256
DAS instruction, 3-258
Debug registers, moving value to and from, 3-600
DEC instruction, 3-260, 3-541
Denormalized finite number, 3-409