Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-92 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
B.11 SPECIAL ENCODINGS FOR 64-BIT MODE
The following Pentium, P6, MMX, SSE, SSE2, SSE3 instructions are promoted to
64-bit operation in IA-32e mode by using REX.W. However, these entries are special
cases that do not follow the general rules (specified in Section B.4).
PSIGNW—Packed Sign
Words
mmreg to mmreg 0000 1111:0011 1000: 0000 1001:11 mmreg1 mmreg2
mem to mmreg 0000 1111:0011 1000: 0000 1001: mod mmreg r/m
xmmreg to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1001:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1001: mod xmmreg r/m
Table B-32. Special Case Instructions Promoted Using REX.W
Instruction and Format Encoding
CMOVcc—Conditional Move
register2 to register1 0100 0R0B 0000 1111: 0100 tttn : 11 reg1
reg2
qwordregister2 to qwordregister1 0100 1R0B 0000 1111: 0100 tttn : 11
qwordreg1 qwordreg2
memory to register 0100 0RXB 0000 1111 : 0100 tttn : mod reg
r/m
memory64 to qwordregister 0100 1RXB 0000 1111 : 0100 tttn : mod
qwordreg r/m
CVTSD2SI—Convert Scalar Double-Precision
Floating-Point Value to Doubleword Integer
xmmreg to r32 0100 0R0B 1111 0010:0000 1111:0010
1101:11 r32 xmmreg
xmmreg to r64 0100 1R0B 1111 0010:0000 1111:0010
1101:11 r64 xmmreg
mem64 to r32 0100 0R0XB 1111 0010:0000 1111:0010
1101: mod r32 r/m
mem64 to r64 0100 1RXB 1111 0010:0000 1111:0010
1101: mod r64 r/m
Table B-31. Formats and Encodings for SSSE3 Instructions (Contd.)
Instruction and Format Encoding