Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-38 Vol. 2B

INSTRUCTION FORMATS AND ENCODINGS

NOT – One's Complement Negation

qwordregister 0100 000B 1111 0111 : 11 010 qwordreg

memory 0100 00XB : 1111 011w : mod 010 r/m

memory64 0100 1RXB 1111 0111 : mod 010 r/m

OR – Logical Inclusive OR

register1 to register2 0000 100w : 11 reg1 reg2

byteregister1 to byteregister2 0100 0R0B 0000 1000 : 11 bytereg1

bytereg2

qwordregister1 to qwordregister2 0100 1R0B 0000 1001 : 11 qwordreg1

qwordreg2

register2 to register1 0000 101w : 11 reg1 reg2

byteregister2 to byteregister1 0100 0R0B 0000 1010 : 11 bytereg1

bytereg2

qwordregister2 to qwordregister1 0100 0R0B 0000 1011 : 11 qwordreg1

qwordreg2

memory to register 0000 101w : mod reg r/m

memory8 to byteregister 0100 0RXB 0000 1010 : mod bytereg r/m

memory8 to qwordregister 0100 0RXB 0000 1011 : mod qwordreg r/m

byteregister to memory8 0100 0RXB 0000 1000 : mod bytereg r/m

qwordregister to memory64 0100 1RXB 0000 1001 : mod qwordreg r/m

immediate to register 1000 00sw : 11 001 reg : imm

immediate8 to byteregister 0100 000B 1000 0000 : 11 001 bytereg :

imm8

immediate32 to qwordregister 0100 000B 1000 0001 : 11 001 qwordreg :

imm32

immediate8 to qwordregister 0100 000B 1000 0011 : 11 001 qwordreg :

imm8

immediate to AL, AX, or EAX 0000 110w : imm

immediate64 to RAX 0100 1000 0000 1101 : imm64

immediate to memory 1000 00sw : mod 001 r/m : imm

Table B-15. General Purpose Instruction Formats and Encodings

for 64-Bit Mode (Contd.)

Instruction and Format Encoding