Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-180 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PSRLDQ—Shift Double Quadword Right Logical
Description
Shifts the destination operand (first operand) to the right by the number of bytes
specified in the count operand (second operand). The empty high-order bytes are
cleared (set to all 0s). If the value specified by the count operand is greater than 15,
the destination operand is set to all 0s. The destination operand is an XMM register.
The count operand is an 8-bit immediate.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
TEMP ← COUNT;
IF (TEMP
> 15) THEN TEMP ← 16; FI;
DEST ← DEST
>> (temp ∗ 8);
Intel C/C++ Compiler Intrinsic Equivalents
PSRLDQ __m128i _mm_srli_si128 ( __m128i a, int imm)
Flags Affected
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
#NM If CR0.TS[bit 3] = 1.
Real-Address Mode Exceptions
Same exceptions as in Protected Mode.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
66 0F 73 /3 ib PSRLDQ
xmm1, imm8
Valid Valid Shift xmm1 right by imm8 while
shifting in 0s.