Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-101
INSTRUCTION FORMATS AND ENCODINGS
FSTSW – Store Status Word into Memory 11011 101 : mod 111 r/m
FSUB – Subtract
ST(0) ← ST(0) – 32-bit memory 11011 000 : mod 100 r/m
ST(0) ← ST(0) – 64-bit memory 11011 100 : mod 100 r/m
ST(d) ← ST(0) – ST(i) 11011 d00 : 1110 R ST(i)
FSUBP – Subtract and Pop
ST(0) ← ST(0) – ST(i) 11011 110 : 1110 1 ST(i)
FSUBR – Reverse Subtract
ST(0) ← 32-bit memory – ST(0) 11011 000 : mod 101 r/m
ST(0) ← 64-bit memory – ST(0) 11011 100 : mod 101 r/m
ST(d) ← ST(i) – ST(0) 11011 d00 : 1110 R ST(i)
FSUBRP – Reverse Subtract and Pop
ST(i) ← ST(i) – ST(0) 11011 110 : 1110 0 ST(i)
FTST – Test 11011 001 : 1110 0100
FUCOM – Unordered Compare Real 11011 101 : 1110 0 ST(i)
FUCOMP – Unordered Compare Real and Pop 11011 101 : 1110 1 ST(i)
FUCOMPP – Unordered Compare Real and Pop
Twice
11011 010 : 1110 1001
FUCOMI – Unorderd Compare Real and Set
EFLAGS
11011 011 : 11 101 ST(i)
FUCOMIP – Unorderd Compare Real, Set EFLAGS,
and Pop
11011 111 : 11 101 ST(i)
FXAM – Examine 11011 001 : 1110 0101
FXCH – Exchange ST(0) and ST(i) 11011 001 : 1100 1 ST(i)
FXTRACT – Extract Exponent and Significand 11011 001 : 1111 0100
FYL2X – ST(1) × log
2
(ST(0)) 11011 001 : 1111 0001
FYL2XP1 – ST(1) × log
2
(ST(0) + 1.0) 11011 001 : 1111 1001
FWAIT – Wait until FPU Ready 1001 1011
Table B-34. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format Encoding