Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-77
INSTRUCTION FORMATS AND ENCODINGS
UNPCKLPD—Unpack and Interleave
Low Packed Double-Precision
Floating-Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0001 0100:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0001 0100: mod xmmreg r/m
XORPD—Bitwise Logical OR of
Double-Precision Floating-Point
Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 0111:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0101 0111: mod xmmreg r/m
Table B-26. Formats and Encodings of SSE2 Integer Instructions
Instruction and Format Encoding
MOVD—Move Doubleword
reg to xmmeg 0110 0110:0000 1111:0110 1110: 11 xmmreg reg
reg from xmmreg 0110 0110:0000 1111:0111 1110: 11 xmmreg reg
mem to xmmreg 0110 0110:0000 1111:0110 1110: mod xmmreg r/m
mem from xmmreg 0110 0110:0000 1111:0111 1110: mod xmmreg r/m
MOVDQA—Move Aligned Double
Quadword
xmmreg to xmmreg 0110 0110:0000 1111:0110 1111:11 xmmreg1
xmmreg2
0110 0110:0000 1111:0111 1111:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0110 1111: mod xmmreg r/m
mem from xmmreg 0110 0110:0000 1111:0111 1111: mod xmmreg r/m
MOVDQU—Move Unaligned Double
Quadword
xmmreg to xmmreg 1111 0011:0000 1111:0110 1111:11 xmmreg1
xmmreg2
1111 0011:0000 1111:0111 1111:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:0000 1111:0110 1111: mod xmmreg r/m
Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format Encoding