Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-66 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
UCOMISS—Unordered Compare Scalar
Ordered Single-Precision Floating-Point
Values and Set EFLAGS
xmmreg to xmmreg 0000 1111:0010 1110:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0010 1110 mod xmmreg r/m
UNPCKHPS—Unpack and Interleave
High Packed Single-Precision Floating-
Point Values
xmmreg to xmmreg 0000 1111:0001 0101:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0001 0101 mod xmmreg r/m
UNPCKLPS—Unpack and Interleave Low
Packed Single-Precision Floating-Point
Values
xmmreg to xmmreg 0000 1111:0001 0100:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0001 0100 mod xmmreg r/m
XORPS—Bitwise Logical XOR of Single-
Precision Floating-Point Values
xmmreg to xmmreg 0000 1111:0101 0111:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 0111 mod xmmreg r/m
Table B-22. Formats and Encodings of SSE Integer Instructions
Instruction and Format Encoding
PAVGB/PAVGW—Average Packed Integers
mmreg to mmreg 0000 1111:1110 0000:11 mmreg1 mmreg2
0000 1111:1110 0011:11 mmreg1 mmreg2
mem to mmreg 0000 1111:1110 0000 mod mmreg r/m
0000 1111:1110 0011 mod mmreg r/m
PEXTRW—Extract Word
mmreg to reg32, imm8 0000 1111:1100 0101:11 r32 mmreg: imm8
PINSRW—Insert Word
reg32 to mmreg, imm8 0000 1111:1100 0100:11 mmreg r32: imm8
m16 to mmreg, imm8 0000 1111:1100 0100 mod mmreg r/m:
imm8
Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.)
Instruction and Format Encoding