Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-74 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PHADDD with 64-bit operands :
mm1[31-0] = mm1[63-32] + mm1[31-0];
mm1[63-32] = mm2/m64[63-32] + mm2/m64[31-0];
PHADDD with 128-bit operands:
xmm1[31-0] = xmm1[63-32] + xmm1[31-0];
xmm1[63-32] = xmm1[127-96] + xmm1[95-64];
xmm1[95-64] = xmm2/m128[63-32] + xmm2/m128[31-0];
xmm1[127-96] = xmm2/m128[127-96] + xmm2/m128[95-64];
Intel C/C++ Compiler Intrinsic Equivalents
PHADDW __m64 _mm_hadd_pi16 (__m64 a, __m64 b)
PHADDW __m128i _mm_hadd_epi16 (__m128i a, __m128i b)
PHADDD __m64 _mm_hadd_pi32 (__m64 a, __m64 b)
PHADDD __m128i _mm_hadd_epi32 (__m128i a, __m128i b)
Protected Mode Exceptions
#GP(0): If a memory operand effective address is outside the CS, DS,
ES, FS or GS segments.
(128-bit operations only) If not aligned on 16-byte boundary,
regardless of segment.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#PF(fault-code) If a page fault occurs.
#UD If CR0.EM(bit 2)= 1.
(128-bit operations only) If CR4.OSFXSR(bit 9) = 0.
If CPUID.SSSE3(ECX bit 9) = 0.
#NM If TS bit in CR0 is set.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#AC(0) (64-bit operations only) If alignment checking is enabled and
unaligned memory reference is made while the current privilege
level is 3.
Real Mode Exceptions
#GP(0) If any part of the operand lies outside of the effective address
space from 0 to 0FFFFH.
(128-bit operations only) If not aligned on 16-byte boundary,
regardless of segment.