Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B INDEX-3
INDEX
DF (direction) flag, EFLAGS register, 3-106, 3-136,
3-462, 3-544, 3-655, 4-18, 4-287, 4-331
Displacement (operand addressing), 2-4
DIV instruction, 3-262
Divide error exception (#DE), 3-262
DIVPD instruction, 3-266
DIVPS instruction, 3-269
DIVSD instruction, 3-272
DIVSS instruction, 3-275
DS register, 3-135, 3-522, 3-543, 3-654, 4-17
E
EDI register, 4-286, 4-331, 4-337
Effective address, 3-528
EFLAGS register
condition codes, 3-119, 3-301, 3-307
flags affected by instructions, 3-14
loading, 3-511
popping, 4-136
popping on return from interrupt, 3-484
pushing, 4-220
pushing on interrupts, 3-466
saving, 4-273
status flags, 3-122, 3-498, 4-292, 4-373
EIP register, 3-87, 3-466, 3-484, 3-502
EMMS instruction, 3-278
Encodings
See machine instructions, opcodes
ENTER instruction, 3-280
ES register, 3-522, 4-17, 4-286, 4-337
ESI register, 3-135, 3-543, 3-544, 3-654, 4-17, 4-331
ESP register, 3-87, 4-128
Exceptions
BOUND range exceeded (#BR), 3-65
notation, 1-6
overflow exception (#OF), 3-465
returning from, 3-484
Exponent, extracting from floating-point number,
3-426
Extract exponent and significand, x87 FPU operation,
3-426
F
F2XM1 instruction, 3-284, 3-426
FABS instruction, 3-286
FADD instruction, 3-288
FADDP instruction, 3-288
Far pointer, loading, 3-522
Far return, RET instruction, 4-253
FBLD instruction, 3-292
FBSTP instruction, 3-294
FCHS instruction, 3-297
FCLEX instruction, 3-299
FCMOVcc instructions, 3-301
FCOM instruction, 3-303
FCOMI instruction, 3-307
FCOMIP instruction, 3-307
FCOMP instruction, 3-303
FCOMPP instruction, 3-303
FCOS instruction, 3-310
FDECSTP instruction, 3-312
FDIV instruction, 3-314
FDIVP instruction, 3-314
FDIVR instruction, 3-318
FDIVRP instruction, 3-318
Feature information, processor, 3-160
FFREE instruction, 3-322
FIADD instruction, 3-288
FICOM instruction, 3-323
FICOMP instruction, 3-323
FIDIV instruction, 3-314
FIDIVR instruction, 3-318
FILD instruction, 3-326
FIMUL instruction, 3-349
FINCSTP instruction, 3-328
FINIT instruction, 3-330
FINIT/FNINIT instructions, 3-371
FIST instruction, 3-332
FISTP instruction, 3-332
FISTTP instruction, 3-336
FISUB instruction, 3-396
FISUBR instruction, 3-400
FLD instruction, 3-339
FLD1 instruction, 3-342
FLDCW instruction, 3-344
FLDENV instruction, 3-346
FLDL2E instruction, 3-342
FLDL2T instruction, 3-342
FLDLG2 instruction, 3-342
FLDLN2 instruction, 3-342
FLDPI instruction, 3-342
FLDZ instruction, 3-342
Floating point instructions
machine encodings, B-96
Floating-point exceptions
SSE and SSE2 SIMD, 3-17
x87 FPU, 3-17
Flushing
caches, 3-480, 4-399
TLB entry, 3-482
FMUL instruction, 3-349
FMULP instruction, 3-349
FNCLEX instruction, 3-299
FNINIT instruction, 3-330
FNOP instruction, 3-353
FNSAVE instruction, 3-371
FNSTCW instruction, 3-387
FNSTENV instruction, 3-346, 3-390
FNSTSW instruction, 3-393
FPATAN instruction, 3-354
FPREM instruction, 3-357
FPREM1 instruction, 3-360
FPTAN instruction, 3-363
FRNDINT instruction, 3-366