Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-98 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
ST(0) ← ST(0) ÷ 64-bit memory 11011 100 : mod 110 r/m
ST(d) ← ST(0) ÷ ST(i) 11011 d00 : 1111 R ST(i)
FDIVP – Divide and Pop
ST(0) ← ST(0) ÷ ST(i) 11011 110 : 1111 1 ST(i)
FDIVR – Reverse Divide
ST(0) ← 32-bit memory ÷ ST(0) 11011 000 : mod 111 r/m
ST(0) ← 64-bit memory ÷ ST(0) 11011 100 : mod 111 r/m
ST(d) ← ST(i) ÷ ST(0) 11011 d00 : 1111 R ST(i)
FDIVRP – Reverse Divide and Pop
ST(0) ¨ ST(i) ÷ ST(0) 11011 110 : 1111 0 ST(i)
FFREE – Free ST(i) Register 11011 101 : 1100 0 ST(i)
FIADD – Add Integer
ST(0) ← ST(0) + 16-bit memory 11011 110 : mod 000 r/m
ST(0) ← ST(0) + 32-bit memory 11011 010 : mod 000 r/m
FICOM – Compare Integer
16-bit memory 11011 110 : mod 010 r/m
32-bit memory 11011 010 : mod 010 r/m
FICOMP – Compare Integer and Pop
16-bit memory 11011 110 : mod 011 r/m
32-bit memory 11011 010 : mod 011 r/m
FIDIV
ST(0) ← ST(0) ÷ 16-bit memory 11011 110 : mod 110 r/m
ST(0) ← ST(0) ÷ 32-bit memory 11011 010 : mod 110 r/m
FIDIVR
ST(0) ← 16-bit memory ÷ ST(0) 11011 110 : mod 111 r/m
ST(0) ← 32-bit memory ÷ ST(0) 11011 010 : mod 111 r/m
FILD – Load Integer
16-bit memory 11011 111 : mod 000 r/m
32-bit memory 11011 011 : mod 000 r/m
64-bit memory 11011 111 : mod 101 r/m
Table B-34. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format Encoding