Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-72 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
CVTSD2SS—Covert Scalar Double-
Precision Floating-Point Value to
Scalar Single-Precision Floating-Point
Value
xmmreg to xmmreg 1111 0010:0000 1111:0101 1010:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0010:0000 1111:0101 1010: mod xmmreg r/m
CVTSS2SD—Covert Scalar Single-
Precision Floating-Point Value to
Scalar Double-Precision Floating-
Point Value
xmmreg to xmmreg 1111 0011:0000 1111:0101 1010:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:00001 111:0101 1010: mod xmmreg r/m
CVTPD2DQ—Convert Packed Double-
Precision Floating-Point Values to
Packed Doubleword Integers
xmmreg to xmmreg 1111 0010:0000 1111:1110 0110:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0010:0000 1111:1110 0110: mod xmmreg r/m
CVTTPD2DQ—Convert With
Truncation Packed Double-Precision
Floating-Point Values to Packed
Doubleword Integers
xmmreg to xmmreg 0110 0110:0000 1111:1110 0110:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:1110 0110: mod xmmreg r/m
CVTDQ2PD—Convert Packed
Doubleword Integers to Packed
Single-Precision Floating-Point Values
xmmreg to xmmreg 1111 0011:0000 1111:1110 0110:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:0000 1111:1110 0110: mod xmmreg r/m
CVTPS2DQ—Convert Packed Single-
Precision Floating-Point Values to
Packed Doubleword Integers
xmmreg to xmmreg 0110 0110:0000 1111:0101 1011:11 xmmreg1
xmmreg2
Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format Encoding