Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-30 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
immediate32 with RAX 0100 1000 0011 1101 : imm32
immediate with memory 0100 00XB 1000 00sw : mod 111 r/m : imm
immediate32 with memory64 0100 1RXB 1000 0001 : mod 111 r/m : imm64
immediate8 with memory64 0100 1RXB 1000 0011 : mod 111 r/m : imm8
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ –
Compare String Operands
compare string operands [ X at DS:(E)SI with Y
at ES:(E)DI ]
1010 011w
qword at address RSI with qword at address
RDI
0100 1000 1010 0111
CMPXCHG – Compare and Exchange
register1, register2 0000 1111 : 1011 000w : 11 reg2 reg1
byteregister1, byteregister2 0100 000B 0000 1111 : 1011 0000 : 11
bytereg2 reg1
qwordregister1, qwordregister2 0100 100B 0000 1111 : 1011 0001 : 11
qwordreg2 reg1
memory, register 0000 1111 : 1011 000w : mod reg r/m
memory8, byteregister 0100 00XB 0000 1111 : 1011 0000 : mod
bytereg r/m
memory64, qwordregister 0100 10XB 0000 1111 : 1011 0001 : mod
qwordreg r/m
CPUID – CPU Identification 0000 1111 : 1010 0010
CQO – Sign-Extend RAX 0100 1000 1001 1001
CWD – Convert Word to Doubleword 1001 1001
CWDE – Convert Word to Doubleword 1001 1000
DEC – Decrement by 1
register 0100 000B 1111 111w : 11 001 reg
qwordregister 0100 100B 1111 1111 : 11 001 qwordreg
memory 0100 00XB 1111 111w : mod 001 r/m
memory64 0100 10XB 1111 1111 : mod 001 r/m
DIV – Unsigned Divide
AL, AX, or EAX by register 0100 000B 1111 011w : 11 110 reg
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding