Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-59
INSTRUCTION SET REFERENCE, N-Z
PAVGB instruction with 128-bit operands:
SRC[7:0) ← (SRC[7:0) + DEST[7:0) + 1) >> 1; (* Temp sum before shifting is 9 bits *)
(* Repeat operation performed for bytes 2 through 14 *)
SRC[63:56) ← (SRC[63:56) + DEST[63:56) + 1) >> 1;
PAVGW instruction with 128-bit operands:
SRC[15:0) ← (SRC[15:0) + DEST[15:0) + 1) >> 1; (* Temp sum before shifting is 17 bits *)
(* Repeat operation performed for words 2 through 6 *)
SRC[127:48) ← (SRC[127:112) + DEST[127:112) + 1) >> 1;
Intel C/C++ Compiler Intrinsic Equivalent
PAVGB __m64_mm_avg_pu8 (__m64 a, __m64 b)
PAVGW __m64_mm_avg_pu16 (__m64 a, __m64 b)
PAVGB __m128i _mm_avg_epu8 ( __m128i a, __m128i b)
PAVGW __m128i _mm_avg_epu16 ( __m128i a, __m128i b)
Flags Affected
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
(128-bit operations only) If a memory operand is not aligned on
a 16-byte boundary, regardless of segment.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#UD If CR0.EM[bit 2] = 1.
(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.
(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.
#NM If CR0.TS[bit 3] = 1.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#PF(fault-code) If a page fault occurs.
#AC(0) (64-bit operations only) If alignment checking is enabled and an
unaligned memory reference is made while the current privilege
level is 3.