Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-37

INSTRUCTION FORMATS AND ENCODINGS

byteregister2 to qwordregister1 (sign-extend) 0100 1R0B 0000 1111 : 1011 1110 : 11

quadreg1 bytereg2

wordregister2 to qwordregister1 0100 1R0B 0000 1111 : 1011 1111 : 11

quadreg1 wordreg2

dwordregister2 to qwordregister1 0100 1R0B 0110 0011 : 11 quadreg1

dwordreg2

memory to register 0100 0RXB : 0000 1111 : 1011 111w : mod

reg r/m

memory8 to qwordregister (sign-extend) 0100 1RXB 0000 1111 : 1011 1110 : mod

qwordreg r/m

memory16 to qwordregister 0100 1RXB 0000 1111 : 1011 1111 : mod

qwordreg r/m

memory32 to qwordregister 0100 1RXB 0110 0011 : mod qwordreg r/m

MOVZX – Move with Zero-Extend

register2 to register1 0100 0R0B : 0000 1111 : 1011 011w : 11

reg1 reg2

dwordregister2 to qwordregister1 0100 1R0B 0000 1111 : 1011 0111 : 11

qwordreg1 dwordreg2

memory to register 0100 0R0B : 0000 1111 : 1011 011w : mod

reg r/m

memory32 to qwordregister 0100 1R0B 0000 1111 : 1011 0111 : mod

qwordreg r/m

MUL – Unsigned Multiply

AL, AX, or EAX with register 0100 000B : 1111 011w : 11 100 reg

RAX with qwordregister (to RDX:RAX) 0100 100B 1111 0111 : 11 100 qwordreg

AL, AX, or EAX with memory 0100 00XB 1111 011w : mod 100 r/m

RAX with memory64 (to RDX:RAX) 0100 10XB 1111 0111 : mod 100 r/m

NEG – Two's Complement Negation

qwordregister 0100 100B 1111 0111 : 11 011 qwordreg

memory 0100 00XB : 1111 011w : mod 011 r/m

memory64 0100 10XB 1111 0111 : mod 011 r/m

NOP – No Operation 1001 0000

Table B-15. General Purpose Instruction Formats and Encodings

for 64-Bit Mode (Contd.)

Instruction and Format Encoding