Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-401
INSTRUCTION SET REFERENCE, N-Z
WRMSR—Write to Model Specific Register
Description
In legacy and compatibility mode, writes the contents of registers EDX:EAX into the
64-bit model specific register (MSR) specified by the ECX register. The value loaded
into the ECX register is the address of the MSR. The contents of the EDX register are
copied to high-order 32 bits of the selected MSR and the contents of the EAX register
are copied to low-order 32 bits of the MSR. Undefined or reserved bits in an MSR
should be set to values previously read.
This instruction must be executed at privilege level 0 or in real-address mode; other-
wise, a general protection exception #GP(0) is generated. Specifying a reserved or
unimplemented MSR address in ECX will also cause a general protection exception.
The processor will also generate a general protection exception if software attempts
to write to bits in a reserved MSR.
When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated.
This includes global entries (see “Translation Lookaside Buffers (TLBs)” in Chapter 3
of the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).
MSRs control functions for testability, execution tracing, performance-monitoring
and machine check errors. Appendix B, “Model-Specific Registers (MSRs)”, in the
Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, lists all
MSRs that can be read with this instruction and their addresses. Note that each
processor family has its own set of MSRs.
The WRMSR instruction is a serializing instruction (see “Serializing Instructions” in
Chapter 7 of the Intel
®
64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A).
The CPUID instruction should be used to determine whether MSRs are supported
(EDX[5]=1) before using this instruction.
In 64-bit mode, operation is the same as legacy mode, except that targeted registers
are updated by MSR[63:32] = RDX[31:0], MSR[31:0] = RAX[31:0].
IA-32 Architecture Compatibility
The MSRs and the ability to read them with the WRMSR instruction were introduced
into the IA-32 architecture with the Pentium processor. Execution of this instruction
by an IA-32 processor earlier than the Pentium processor results in an invalid opcode
exception #UD.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F 30 WRMSR Valid Valid Write the value in EDX:EAX to MSR
specified by ECX.
REX.W + 0F
30
WRMSR Valid N.E. Write the value in RDX[31:0]:
RAX[31:0] to MSR specified by RCX.