Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-82 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
POR—Bitwise Or
xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 1011: 11 xmmreg1
xmmreg2
xmemory to xmmreg 0110 0110:0000 1111:1110 1011: mod xmmreg r/m
PSADBW—Compute Sum of Absolute
Differences
xmmreg to xmmreg 0110 0110:0000 1111:1111 0110:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:1111 0110: mod xmmreg r/m
PSHUFLW—Shuffle Packed Low
Words
xmmreg to xmmreg, imm8 1111 0010:0000 1111:0111 0000:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8 1111 0010:0000 1111:0111 0000:11 mod xmmreg
r/m: imm8
PSHUFHW—Shuffle Packed High
Words
xmmreg to xmmreg, imm8 1111 0011:0000 1111:0111 0000:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8 1111 0011:0000 1111:0111 0000:11 mod xmmreg
r/m: imm8
PSHUFD—Shuffle Packed
Doublewords
xmmreg to xmmreg, imm8 0110 0110:0000 1111:0111 0000:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8 0110 0110:0000 1111:0111 0000:11 mod xmmreg
r/m: imm8
PSLLDQ—Shift Double Quadword Left
Logical
xmmreg, imm8 0110 0110:0000 1111:0111 0011:11 111 xmmreg:
imm8
PSLL—Packed Shift Left Logical
xmmreg1 by xmmreg2 0110 0110:0000 1111:1111 00gg: 11 xmmreg1
xmmreg2
xmmreg by memory 0110 0110:0000 1111:1111 00gg: mod xmmreg r/m
Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format Encoding