Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-70 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
mem to xmmreg 0110 0110:0000 1111:0101 0101: mod xmmreg r/m
ANDPD—Bitwise Logical AND of Packed
Double-Precision Floating-Point Values
xmmreg to xmmreg 0110 0110:0000 1111:0101 0100:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0101 0100: mod xmmreg r/m
CMPPD—Compare Packed Double-
Precision Floating-Point Values
xmmreg to xmmreg, imm8 0110 0110:0000 1111:1100 0010:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8 0110 0110:0000 1111:1100 0010: mod xmmreg r/m:
imm8
CMPSD—Compare Scalar Double-
Precision Floating-Point Values
xmmreg to xmmreg, imm8 1111 0010:0000 1111:1100 0010:11 xmmreg1
xmmreg2: imm8
mem to xmmreg, imm8 11110 010:0000 1111:1100 0010: mod xmmreg r/m:
imm8
COMISD—Compare Scalar Ordered
Double-Precision Floating-Point
Values and Set EFLAGS
xmmreg to xmmreg 0110 0110:0000 1111:0010 1111:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0010 1111: mod xmmreg r/m
CVTPI2PD—Convert Packed
Doubleword Integers to Packed
Double-Precision Floating-Point
Values
mmreg to xmmreg 0110 0110:0000 1111:0010 1010:11 xmmreg1
mmreg1
mem to xmmreg 0110 0110:0000 1111:0010 1010: mod xmmreg r/m
CVTPD2PI—Convert Packed Double-
Precision Floating-Point Values to
Packed Doubleword Integers
xmmreg to mmreg 0110 0110:0000 1111:0010 1101:11 mmreg1
xmmreg1
mem to mmreg 0110 0110:0000 1111:0010 1101: mod mmreg r/m
Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.)
Instruction and Format Encoding