Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-45
INSTRUCTION FORMATS AND ENCODINGS
immediate8 to memory64 0100 10XB 1000 0011 : mod 011 r/m : imm8
SCAS/SCASB/SCASW/SCASD – Scan String
scan string 1010 111w
scan string (compare AL with byte at RDI) 0100 1000 1010 1110
scan string (compare RAX with qword at RDI) 0100 1000 1010 1111
SETcc – Byte Set on Condition
register 0100 000B 0000 1111 : 1001 tttn : 11 000
reg
register 0100 0000 0000 1111 : 1001 tttn : 11 000
reg
memory 0100 00XB 0000 1111 : 1001 tttn : mod 000
r/m
memory 0100 0000 0000 1111 : 1001 tttn : mod 000
r/m
SGDT – Store Global Descriptor Table Register 0000 1111 : 0000 0001 : mod
A
000 r/m
SHL – Shift Left
register by 1 0100 000B 1101 000w : 11 100 reg
byteregister by 1 0100 000B 1101 0000 : 11 100 bytereg
qwordregister by 1 0100 100B 1101 0001 : 11 100 qwordreg
memory by 1 0100 00XB 1101 000w : mod 100 r/m
memory8 by 1 0100 00XB 1101 0000 : mod 100 r/m
memory64 by 1 0100 10XB 1101 0001 : mod 100 r/m
register by CL 0100 000B 1101 001w : 11 100 reg
byteregister by CL 0100 000B 1101 0010 : 11 100 bytereg
qwordregister by CL 0100 100B 1101 0011 : 11 100 qwordreg
memory by CL 0100 00XB 1101 001w : mod 100 r/m
memory8 by CL 0100 00XB 1101 0010 : mod 100 r/m
memory64 by CL 0100 10XB 1101 0011 : mod 100 r/m
register by immediate count 0100 000B 1100 000w : 11 100 reg : imm8
byteregister by immediate count 0100 000B 1100 0000 : 11 100 bytereg :
imm8
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding