Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

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INSTRUCTION SET REFERENCE, N-Z

PAVGB/PAVGW—Average Packed Integers

Description

Performs a SIMD average of the packed unsigned integers from the source operand

(second operand) and the destination operand (first operand), and stores the results

in the destination operand. For each corresponding pair of data elements in the first

and second operands, the elements are added together, a 1 is added to the tempo-

rary sum, and that result is shifted right one bit position. The source operand can be

an MMX technology register or a 64-bit memory location or it can be an XMM register

or a 128-bit memory location. The destination operand can be an MMX technology

The PAVGB instruction operates on packed unsigned bytes and the PAVGW instruc-

tion operates on packed unsigned words.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Operation

PAVGB instruction with 64-bit operands:

SRC[7:0) ← (SRC[7:0) + DEST[7:0) + 1) >> 1; (* Temp sum before shifting is 9 bits *)

(* Repeat operation performed for bytes 2 through 6 *)

SRC[63:56) ← (SRC[63:56) + DEST[63:56) + 1) >> 1;

PAVGW instruction with 64-bit operands:

SRC[15:0) ← (SRC[15:0) + DEST[15:0) + 1) >> 1; (* Temp sum before shifting is 17 bits *)

(* Repeat operation performed for words 2 and 3 *)

SRC[63:48) ← (SRC[63:48) + DEST[63:48) + 1) >> 1;

Opcode Instruction

64-Bit

Mode

Compat/

Leg Mode Description

0F E0 /r PAVGB mm1,

mm2/m64

Valid Valid Average packed unsigned byte

integers from mm2/m64 and mm1

with rounding.

66 0F E0, /r PAVGB xmm1,

xmm2/m128

Valid Valid Average packed unsigned byte

integers from xmm2/m128 and

xmm1 with rounding.

0F E3 /r PAVGW mm1,