Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-83
INSTRUCTION FORMATS AND ENCODINGS
xmmreg by immediate 0110 0110:0000 1111:0111 00gg: 11 110 xmmreg:
imm8
PSRA—Packed Shift Right Arithmetic
xmmreg1 by xmmreg2 0110 0110:0000 1111:1110 00gg: 11 xmmreg1
xmmreg2
xmmreg by memory 0110 0110:0000 1111:1110 00gg: mod xmmreg r/m
xmmreg by immediate 0110 0110:0000 1111:0111 00gg: 11 100 xmmreg:
imm8
PSRLDQ—Shift Double Quadword
Right Logical
xmmreg, imm8 0110 0110:00001111:01110011:11 011 xmmreg:
imm8
PSRL—Packed Shift Right Logical
xmmxreg1 by xmmxreg2 0110 0110:0000 1111:1101 00gg: 11 xmmreg1
xmmreg2
xmmxreg by memory 0110 0110:0000 1111:1101 00gg: mod xmmreg r/m
xmmxreg by immediate 0110 0110:0000 1111:0111 00gg: 11 010 xmmreg:
imm8
PSUBQ—Subtract Packed Quadword
Integers
mmreg to mmreg 0000 1111:11111 011:11 mmreg1 mmreg2
mem to mmreg 0000 1111:1111 1011: mod mmreg r/m
xmmreg to xmmreg 0110 0110:0000 1111:1111 1011:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:1111 1011: mod xmmreg r/m
PSUB—Subtract With Wrap-around
xmmreg2 from xmmreg1 0110 0110:0000 1111:1111 10gg: 11 xmmreg1
xmmreg2
memory from xmmreg 0110 0110:0000 1111:1111 10gg: mod xmmreg r/m
PSUBS—Subtract Signed With
Saturation
xmmreg2 from xmmreg1 0110 0110:0000 1111:1110 10gg: 11 xmmreg1
xmmreg2
memory from xmmreg 0110 0110:0000 1111:1110 10gg: mod xmmreg r/m
Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format Encoding