Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-47
INSTRUCTION FORMATS AND ENCODINGS
memory by CL 0100 00XB 1101 001w : mod 101 r/m
memory8 by CL 0100 00XB 1101 0010 : mod 101 r/m
memory64 by CL 0100 10XB 1101 0011 : mod 101 r/m
register by immediate count 0100 000B 1100 000w : 11 101 reg : imm8
byteregister by immediate count 0100 000B 1100 0000 : 11 101 reg : imm8
qwordregister by immediate count 0100 100B 1100 0001 : 11 101 reg : imm8
memory by immediate count 0100 00XB 1100 000w : mod 101 r/m : imm8
memory8 by immediate count 0100 00XB 1100 0000 : mod 101 r/m : imm8
memory64 by immediate count 0100 10XB 1100 0001 : mod 101 r/m : imm8
SHRD – Double Precision Shift Right
register by immediate count 0100 0R0B 0000 1111 : 1010 1100 : 11 reg2
reg1 : imm8
qwordregister by immediate8 0100 1R0B 0000 1111 : 1010 1100 : 11
qwordreg2 qwordreg1 : imm8
memory by immediate count 0100 00XB 0000 1111 : 1010 1100 : mod reg
r/m : imm8
memory64 by immediate8 0100 1RXB 0000 1111 : 1010 1100 : mod
qwordreg r/m : imm8
register by CL 0100 000B 0000 1111 : 1010 1101 : 11 reg2
reg1
qwordregister by CL 0100 1R0B 0000 1111 : 1010 1101 : 11
qwordreg2 qwordreg1
memory by CL 0000 1111 : 1010 1101 : mod reg r/m
memory64 by CL 0100 1RXB 0000 1111 : 1010 1101 : mod
qwordreg r/m
SIDT – Store Interrupt Descriptor Table
Register
0000 1111 : 0000 0001 : mod
A
001 r/m
SLDT – Store Local Descriptor Table Register
to register 0100 000B 0000 1111 : 0000 0000 : 11 000
reg
to memory 0100 00XB 0000 1111 : 0000 0000 : mod
000 r/m
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding