Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-34 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
LMSW – Load Machine Status Word
from register 0100 000B : 0000 1111 : 0000 0001 : 11 110
reg
from memory 0100 00XB :0000 1111 : 0000 0001 : mod
110 r/m
LOCK – Assert LOCK# Signal Prefix 1111 0000
LODS/LODSB/LODSW/LODSD/LODSQ – Load
String Operand
at DS:(E)SI to AL/EAX/EAX 1010 110w
at (R)SI to RAX 0100 1000 1010 1101
LOOP – Loop Count
if count != 0, 8-bit displacement 1110 0010
if count !=0, RIP + 8-bit displacement sign-
extended to 64-bits
0100 1000 1110 0010
LOOPE – Loop Count while Zero/Equal
if count != 0 & ZF =1, 8-bit displacement 1110 0001
if count !=0 & ZF = 1, RIP + 8-bit displacement
sign-extended to 64-bits
0100 1000 1110 0001
LOOPNE/LOOPNZ – Loop Count while not
Zero/Equal
if count != 0 & ZF = 0, 8-bit displacement 1110 0000
if count !=0 & ZF = 0, RIP + 8-bit displacement
sign-extended to 64-bits
0100 1000 1110 0000
LSL – Load Segment Limit
from register 0000 1111 : 0000 0011 : 11 reg1 reg2
from qwordregister 0100 1R00 0000 1111 : 0000 0011 : 11
qwordreg1 reg2
from memory16 0000 1111 : 0000 0011 : mod reg r/m
from memory64 0100 1RXB 0000 1111 : 0000 0011 : mod
qwordreg r/m
LSS – Load Pointer to SS
SS:r16/r32 with far pointer from memory 0100 0RXB : 0000 1111 : 1011 0010 : mod
A
reg r/m
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding