Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-21
INSTRUCTION FORMATS AND ENCODINGS
register by CL 0000 1111 : 1010 0101 : 11 reg2 reg1
memory by CL 0000 1111 : 1010 0101 : mod reg r/m
SHR – Shift Right
register by 1 1101 000w : 11 101 reg
memory by 1 1101 000w : mod 101 r/m
register by CL 1101 001w : 11 101 reg
memory by CL 1101 001w : mod 101 r/m
register by immediate count 1100 000w : 11 101 reg : imm8 data
memory by immediate count 1100 000w : mod 101 r/m : imm8 data
SHRD – Double Precision Shift Right
register by immediate count 0000 1111 : 1010 1100 : 11 reg2 reg1 : imm8
memory by immediate count 0000 1111 : 1010 1100 : mod reg r/m : imm8
register by CL 0000 1111 : 1010 1101 : 11 reg2 reg1
memory by CL 0000 1111 : 1010 1101 : mod reg r/m
SIDT – Store Interrupt Descriptor Table
Register
0000 1111 : 0000 0001 : mod
A
001 r/m
SLDT – Store Local Descriptor Table Register
to register 0000 1111 : 0000 0000 : 11 000 reg
to memory 0000 1111 : 0000 0000 : mod 000 r/m
SMSW – Store Machine Status Word
to register 0000 1111 : 0000 0001 : 11 100 reg
to memory 0000 1111 : 0000 0001 : mod 100 r/m
STC – Set Carry Flag 1111 1001
STD – Set Direction Flag 1111 1101
STI – Set Interrupt Flag 1111 1011
STOS/STOSB/STOSW/STOSD – Store String
Data
1010 101w
STR – Store Task Register
to register 0000 1111 : 0000 0000 : 11 001 reg
to memory 0000 1111 : 0000 0000 : mod 001 r/m
Table B-13. General Purpose Instruction Formats and Encodings
for Non-64-Bit Modes (Contd.)
Instruction and Format Encoding