Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-48 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PALIGNR — Packed Align Right
Description
PALIGNR concatenates the destination operand (the first operand) and the source
operand (the second operand) into an intermediate composite, shifts the composite
at byte granularity to the right by a constant immediate, and extracts the right-
aligned result into the destination. The first and the second operands can be an MMX
or an XMM register. The immediate value is considered unsigned. Immediate shift
counts larger than the 2L (i.e. 32 for 128-bit operands, or 16 for 64-bit operands)
produce a zero result. Both operands can be MMX register or XMM registers. When
the source operand is a 128-bit memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated.
In 64-bit mode, use the REX prefix to access additional registers.
Operation
PALIGNR with 64-bit operands:
temp1[127:0] = CONCATENATE(DEST,SRC)>>(imm8*8)
DEST[63:0] = temp1[63:0]
PALIGNR with 128-bit operands:
temp1[255:0] = CONCATENATE(DEST,SRC)>>(imm8*8)
DEST[127:0] = temp1[127:0]
Intel C/C++ Compiler Intrinsic Equivalents
PALIGNR __m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)
PALIGNR __m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F 3A 0F PALIGNR mm1,
mm2/m64, imm8
Valid Valid Concatenate destination and
source operands, extract byte-
aligned result shifted to the right
by constant into mm1.
66 0F 3A 0F PALIGNR xmm1,
xmm2/m128,
imm8
Valid Valid Concatenate destination and
source operands, extract byte-
aligned result shifted to the right
by constant into xmm1