Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-10 Vol. 2B

INSTRUCTION FORMATS AND ENCODINGS

immediate to AL, AX, or EAX 0000 010w : immediate data

immediate to memory 1000 00sw : mod 000 r/m : immediate data

AND – Logical AND

register1 to register2 0010 000w : 11 reg1 reg2

register2 to register1 0010 001w : 11 reg1 reg2

memory to register 0010 001w : mod reg r/m

immediate to register 1000 00sw : 11 100 reg : immediate data

immediate to AL, AX, or EAX 0010 010w : immediate data

immediate to memory 1000 00sw : mod 100 r/m : immediate data

ARPL – Adjust RPL Field of Selector

from register 0110 0011 : 11 reg1 reg2

from memory 0110 0011 : mod reg r/m

BOUND – Check Array Against Bounds 0110 0010 : mod

reg r/m

BSF – Bit Scan Forward

register1, register2 0000 1111 : 1011 1100 : 11 reg1 reg2

memory, register 0000 1111 : 1011 1100 : mod reg r/m

BSR – Bit Scan Reverse

register1, register2 0000 1111 : 1011 1101 : 11 reg1 reg2

memory, register 0000 1111 : 1011 1101 : mod reg r/m

BSWAP – Byte Swap 0000 1111 : 1100 1 reg

BT – Bit Test

data

memory, immediate 0000 1111 : 1011 1010 : mod 100 r/m : imm8

data

register1, register2 0000 1111 : 1010 0011 : 11 reg2 reg1

memory, reg 0000 1111 : 1010 0011 : mod reg r/m

BTC – Bit Test and Complement

data

Table B-13. General Purpose Instruction Formats and Encodings

for Non-64-Bit Modes (Contd.)

Instruction and Format Encoding