Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-246 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
RDTSC—Read Time-Stamp Counter
Description
In legacy, compatibility and default 64-bit mode; loads the current value of the
processor’s time-stamp counter into the EDX:EAX registers. The time-stamp counter
is contained in a 64-bit MSR. The high-order 32 bits of the MSR are loaded into the
EDX register, and the low-order 32 bits are loaded into the EAX register.
The processor monotonically increments the time-stamp counter MSR every clock
cycle and resets it to 0 whenever the processor is reset. See “Time Stamp Counter”
in Chapter 18 of the Intel
®
64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B, for specific details of the time stamp counter behavior.
When in protected or virtual 8086 mode, the time stamp disable (TSD) flag in
register CR4 restricts the use of the RDTSC instruction as follows. When the TSD flag
is clear, the RDTSC instruction can be executed at any privilege level; when the flag
is set, the instruction can only be executed at privilege level 0. (When in real-address
mode, the RDTSC instruction is always enabled.)
The time-stamp counter can also be read with the RDMSR instruction, when
executing at privilege level 0.
The RDTSC instruction is not a serializing instruction. Thus, it does not necessarily
wait until all previous instructions have been executed before reading the counter.
Similarly, subsequent instructions may begin execution before the read operation is
performed.
This instruction was introduced by the Pentium processor.
In 64-bit mode, RDTSC behavior is unchanged from 32-bit mode. The upper 32 bits
of RAX and RDX are cleared.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 21 of
the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, for
more information about the behavior of this instruction in VMX non-root operation.
Operation
IF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)
THEN
IF 64-Bit Mode
THEN
RAX[31:0] ← TimeStampCounter[31:0];
RAX[63:32] ← 0;
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F 31 RDTSC Valid Valid Read time-stamp counter into
EDX:EAX.