Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-243
INSTRUCTION SET REFERENCE, N-Z
EAX ← IA32_FIXED_CTR(ECX)[30:0];
EDX ← IA32_FIXED_CTR(ECX)[39:32];
ELSE IF (ECX[30:0] in valid range)
EAX ← PMC(ECX[30:0])[31:0];
EDX ← PMC(ECX[30:0])[39:32];
ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
#GP(0);
FI;
(* P6 family processors and Pentium processor with MMX technology *)
IF (ECX
= 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
THEN
EAX ← PMC(ECX)[31:0];
EDX ← PMC(ECX)[39:32];
ELSE (* ECX is not 0 or 1 or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
#GP(0);
FI;
(* Processors with CPUID family 15 *)
IF ((CR4.PCE
= 1) or (CPL = 0) or (CR0.PE = 0))
THEN IF (ECX[30:0]
= 0:17)
THEN IF ECX[31]
= 0
THEN IF 64-Bit Mode
THEN
RAX[31:0] ← PMC(ECX[30:0])[31:0]; (* 40-bit read *)
RAX[63:32] ← 0;
RDX[31:0] ← PMC(ECX[30:0])[39:32];
RDX[63:32] ← 0;
ELSE
EAX ← PMC(ECX[30:0])[31:0]; (* 40-bit read *)
EDX ← PMC(ECX[30:0])[39:32];
FI;
ELSE IF ECX[31]
= 1
THEN IF 64-Bit Mode
THEN
RAX[31:0] ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)
RAX[63:32] ← 0;
RDX ← 0;
ELSE
EAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *)
EDX ← 0;
FI;
FI;
ELSE IF (*64-bit Intel Xeon processor with L3 *)