Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-67
INSTRUCTION SET REFERENCE, N-Z
PCMPGTD instruction with 128-bit operands:
IF DEST[31:0] > SRC[31:0]
THEN DEST[31:0] ← FFFFFFFFH;
ELSE DEST[31:0] ← 0; FI;
(* Continue comparison of 2nd and 3rd doublewords in DEST and SRC *)
IF DEST[63:32] > SRC[63:32]
THEN DEST[63:32] ← FFFFFFFFH;
ELSE DEST[63:32] ← 0; FI;
Intel C/C++ Compiler Intrinsic Equivalents
PCMPGTB __m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)
PCMPGTW __m64 _mm_pcmpgt_pi16 (__m64 m1, __m64 m2)
DCMPGTD __m64 _mm_pcmpgt_pi32 (__m64 m1, __m64 m2)
PCMPGTB __m128i _mm_cmpgt_epi8 ( __m128i a, __m128i b
PCMPGTW __m128i _mm_cmpgt_epi16 ( __m128i a, __m128i b
DCMPGTD __m128i _mm_cmpgt_epi32 ( __m128i a, __m128i b
Flags Affected
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
(128-bit operations only) If a memory operand is not aligned on
a 16-byte boundary, regardless of segment.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#UD If CR0.EM[bit 2] = 1.
128-bit operations will generate #UD only if CR4.OSFXSR[bit 9]
= 0. Execution of 128-bit instructions on a non-SSE2 capable
processor (one that is MMX technology capable) will result in the
instruction operating on the mm registers, not #UD.
#NM If CR0.TS[bit 3] = 1.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#PF(fault-code) If a page fault occurs.