Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-40 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
memory64 0100 W00B
S
: 1111 1111 : mod 110 r/m
immediate8 0110 1010 : imm8
immediate16 0101 0101 : 0110 1000 : imm16
immediate64 0110 1000 : imm64
PUSH – Push Segment Register onto the
Stack
segment register FS,GS 0000 1111: 10 sreg3 000
PUSHF/PUSHFD – Push Flags Register onto
the Stack
1001 1100
RCL – Rotate thru Carry Left
register by 1 0100 000B : 1101 000w : 11 010 reg
qwordregister by 1 0100 100B 1101 0001 : 11 010 qwordreg
memory by 1 0100 00XB : 1101 000w : mod 010 r/m
memory64 by 1 0100 10XB 1101 0001 : mod 010 r/m
register by CL 0100 000B : 1101 001w : 11 010 reg
qwordregister by CL 0100 100B 1101 0011 : 11 010 qwordreg
memory by CL 0100 00XB : 1101 001w : mod 010 r/m
memory64 by CL 0100 10XB 1101 0011 : mod 010 r/m
register by immediate count 0100 000B : 1100 000w : 11 010 reg : imm
qwordregister by immediate count 0100 100B 1100 0001 : 11 010 qwordreg :
imm8
memory by immediate count 0100 00XB : 1100 000w : mod 010 r/m : imm
memory64 by immediate count 0100 10XB 1100 0001 : mod 010 r/m : imm8
RCR – Rotate thru Carry Right
register by 1 0100 000B : 1101 000w : 11 011 reg
qwordregister by 1 0100 100B 1101 0001 : 11 011 qwordreg
memory by 1 0100 00XB : 1101 000w : mod 011 r/m
memory64 by 1 0100 10XB 1101 0001 : mod 011 r/m
register by CL 0100 000B : 1101 001w : 11 011 reg
qwordregister by CL 0100 000B 1101 0010 : 11 011 qwordreg
memory by CL 0100 00XB : 1101 001w : mod 011 r/m
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding