Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

A-4 Vol. 2B
OPCODE MAP
A.2.3 Register Codes
When an opcode requires a specific register as an operand, the register is identified
by name (for example, AX, CL, or ESI). The name indicates whether the register is
64, 32, 16, or 8 bits wide.
A register identifier of the form eXX or rXX is used when register width depends on
the operand-size attribute. eXX is used when 16 or 32-bit sizes are possible; rXX is
used when 16, 32, or 64-bit sizes are possible. For example: eAX indicates that the
AX register is used when the operand-size attribute is 16 and the EAX register is used
when the operand-size attribute is 32. rAX can indicate AX, EAX or RAX.
When the REX.B bit is used to modify the register specified in the reg field of the
opcode, this fact is indicated by adding “/x” to the register name to indicate the addi-
tional possibility. For example, rCX/r9 is used to indicate that the register could either
be rCX or r9. Note that the size of r9 in this case is determined by the operand size
attribute (just as for rCX).
A.2.4 Opcode Look-up Examples for One, Two,
and Three-Byte Opcodes
This section provides examples that demonstrate how opcode maps are used.
A.2.4.1 One-Byte Opcode Instructions
The opcode map for 1-byte opcodes is shown in Table A-2. The opcode map for
1-byte opcodes is arranged by row (the least-significant 4 bits of the hexadecimal
value) and column (the most-significant 4 bits of the hexadecimal value). Each entry
in the table lists one of the following types of opcodes:
• Instruction mnemonics and operand types using the notations listed in Section
A.2
• Opcodes used as an instruction prefix
For each entry in the opcode map that corresponds to an instruction, the rules for
interpreting the byte following the primary opcode fall into one of the following
cases:
• A ModR/M byte is required and is interpreted according to the abbreviations listed
in Section A.1 and Chapter 2, “Instruction Format,” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2A. Operand types are listed
according to notations listed in Section A.2.
• A ModR/M byte is required and includes an opcode extension in the reg field in
the ModR/M byte. Use Table A-6 when interpreting the ModR/M byte.
• Use of the ModR/M byte is reserved or undefined. This applies to entries that
represent an instruction prefix or entries for instructions without operands that
use ModR/M (for example: 60H, PUSHA; 06H, PUSH ES).