Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-335
INSTRUCTION SET REFERENCE, N-Z
STMXCSR—Store MXCSR Register State
Description
Stores the contents of the MXCSR control and status register to the destination
operand. The destination operand is a 32-bit memory location. The reserved bits in
the MXCSR register are stored as 0s.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
m32 ← MXCSR;
Intel C/C++ Compiler Intrinsic Equivalent
_mm_getcsr(void)
Exceptions
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS, or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#UD If CR0.EM[bit 2] = 1.
#NM If CR0.TS[bit 3] = 1.
#AC For unaligned memory reference. To enable #AC exceptions,
three conditions must be true: CR0.AM[bit 18] = 1,
EFLAGS.AC[bit 18] = 1, current CPL = 3.
#UD If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.
Opcode Instruction
64-
Bit
Mode
Compat/
Leg Mode Description
0F AE /3 STMXCSR m32 Valid Valid Store contents of MXCSR register to
m32.