Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B INDEX-5
INDEX
Interrupts
interrupt vector 4, 3-465
returning from, 3-484
software, 3-465
INTn instruction, 3-465
INTO instruction, 3-465
Intrinsics
compiler functional equivalents, C-1
composite, C-15
description of, 3-12
list of, C-1
simple, C-2
INVD instruction, 3-480
INVLPG instruction, 3-482
IOPL (I/O privilege level) field, EFLAGS register, 3-109,
4-220, 4-332
IRET instruction, 3-484
IRETD instruction, 3-484
J
Jcc instructions, 3-495
JMP instruction, 3-501
Jump operation, 3-501
L
L1 Context ID, 3-172
LAHF instruction, 3-511
LAR instruction, 3-513
LDDQU instruction, 3-517
LDMXCSR instruction, 3-520
LDS instruction, 3-522
LDT (local descriptor table), 3-537
LDTR (local descriptor table register), 3-537, 4-313
LEA instruction, 3-528
LEAVE instruction, 3-531
LES instruction, 3-522
LFENCE instruction, 3-533
LFS instruction, 3-522
LGDT instruction, 3-534
LGS instruction, 3-522
LIDT instruction, 3-534
LLDT instruction, 3-537
LMSW instruction, 3-539
Load effective address operation, 3-528
LOCK prefix, 3-28, 3-31, 3-53, 3-77, 3-80, 3-83,
3-148, 3-260, 3-459, 3-541, 4-2, 4-6, 4-9,
4-283, 4-344, 4-403, 4-407, 4-412
Locking operation, 3-541
LODS instruction, 3-543, 4-250
LODSB instruction, 3-543
LODSD instruction, 3-543
LODSQ instruction, 3-543
LODSW instruction, 3-543
Log epsilon, x87 FPU operation, 3-428
Log (base 2), x87 FPU operation, 3-430
LOOP instructions, 3-547
LOOPcc instructions, 3-547
LSL instruction, 3-550
LSS instruction, 3-522
LTR instruction, 3-554
M
Machine check architecture
CPUID flag, 3-175
description, 3-175
Machine instructions
64-bit mode, B-1
condition test (tttn) field, B-7
direction bit (d) field, B-8
floating-point instruction encodings, B-96
general description, B-1
general-purpose encodings, B-9–B-52
legacy prefixes, B-2
MMX encodings, B-54–B-58
opcode fields, B-2
operand size (w) bit, B-5
P6 family encodings, B-59
Pentium processor family encodings, B-53
reg (reg) field, B-3, B-4
REX prefixes, B-2
segment register (sreg) field, B-6
sign-extend (s) bit, B-6
SIMD 64-bit encodings, B-54
special 64-bit encodings, B-92
special fields, B-2
special-purpose register (eee) field, B-7
SSE encodings, B-60–B-68
SSE2 encodings, B-69–B-85
SSE3 encodings, B-86–B-88
SSSE3 encodings, B-88–B-92
VMX encodings, B-102–B-103
See also: opcodes
Machine status word, CR0 register, 3-539, 4-315
MASKMOVDQU instruction, 3-557
MASKMOVQ instruction, 3-560
MAXPD instruction, 3-563
MAXPS instruction, 3-566
MAXSD instruction, 3-569
MAXSS instruction, 3-572
MFENCE instruction, 3-575
MINPD instruction, 3-576
MINPS instruction, 3-579
MINSD instruction, 3-582
MINSS instruction, 3-585
MMX instructions
CPUID flag for technology, 3-175
encodings, B-54
Mod field, instruction format, 2-4
Model & family information, 3-180
ModR/M byte, 2-4
16-bit addressing forms, 2-6
32-bit addressing forms of, 2-7
description of, 2-4