Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

A-12 Vol. 2B
OPCODE MAP
Table A-3. Two-byte Opcode Map: 08H — 7FH (First Byte is 0FH) *
89ABCDEF
0 INVD WBINVD 2-byte Illegal
Opcodes
UD2
1B
NOP Ev
1 Prefetch
1C
(Grp 16
1A
)
NOP Ev
2 movaps
Vps, Wps
movapd (66)
Vpd, Wpd
movaps
Wps, Vps
movapd (66)
Wpd, Vpd
cvtpi2ps
Vps, Qq
cvtsi2ss (F3)
Vss, Ed/q
cvtpi2pd (66)
Vpd, Qq
cvtsi2sd (F2)
Vsd, Ed/q
movntps
Mps, Vps
movntpd (66)
Mpd, Vpd
cvttps2pi
Qq, Wps
cvttss2si (F3)
Gd, Wss
cvttpd2pi (66)
Qdq, Wpd
cvttsd2si (F2)
Gd, Wsd
cvtps2pi
Qq, Wps
cvtss2si (F3)
Gd/q, Wss
cvtpd2pi (66)
Qdq, Wpd
cvtsd2si (F2)
Gd/q, Wsd
ucomiss
Vss, Wss
ucomisd (66)
Vsd, Wsd
comiss
Vps, Wps
comisd (66)
Vsd, Wsd
3 3-byte escape
(Table A-4)
3-byte escape
(Table A-5)
4 CMOVcc(Gv, Ev) - Conditional Move
S NS P/PE NP/PO L/NGE NL/GE LE/NG NLE/G
5 addps
Vps, Wps
addss (F3)
Vss, Wss
addpd (66)
Vpd, Wpd
addsd (F2)
Vsd, Wsd
mulps
Vps, Wps
mulss (F3)
Vss, Wss
mulpd (66)
Vpd, Wpd
mulsd (F2)
Vsd, Wsd
cvtps2pd
Vpd, Wps
cvtss2sd (F3)
Vss, Wss
cvtpd2ps (66)
Vps, Wpd
cvtsd2ss (F2)
Vsd, Wsd
cvtdq2ps
Vps, Wdq
cvtps2dq (66)
Vdq, Wps
cvttps2dq (F3)
Vdq, Wps
subps
Vps, Wps
subss (F3)
Vss, Wss
subpd (66)
Vpd, Wpd
subsd (F2)
Vsd, Wsd
minps
Vps, Wps
minss (F3)
Vss, Wss
minpd (66)
Vpd, Wpd
minsd (F2)
Vsd, Wsd
divps
Vps, Wps
divss (F3)
Vss, Wss
divpd (66)
Vpd, Wpd
divsd (F2)
Vsd, Wsd
maxps
Vps, Wps
maxss (F3)
Vss, Wss
maxpd (66)
Vpd, Wpd
maxsd (F2)
Vsd, Wsd
6 punpckhbw
Pq, Qd
punpckhbw
(66)
Pdq, Qdq
punpckhwd
Pq, Qd
punpckhwd
(66)
Pdq, Qdq
punpckhdq
Pq, Qd
punpckhdq
(66)
Pdq, Qdq
packssdw
Pq, Qd
packssdw (66)
Pdq, Qdq
punpcklqdq
(66)
Vdq, Wdq
punpckhqdq
(66)
Vdq, Wdq
movd/q/
Pd, Ed/q
movd/q (66)
Vdq, Ed/q
movq
Pq, Qq
movdqa (66)
Vdq, Wdq
movdqu (F3)
Vdq, Wdq
7 VMREAD
Ed/q, Gd/q
VMWRITE
Gd/q, Ed/q
haddps(F2)
Vps, Wps
haddpd(66)
Vpd, Wpd
hsubps(F2)
Vps, Wps
hsubpd(66)
Vpd, Wpd
movd/q
Ed/q, Pd
movd/q (66)
Ed/q, Vdq
movq (F3)
Vq, Wq
movq
Qq, Pq
movdqa (66)
Wdq, Vdq
movdqu (F3)
Wdq, Vdq