Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-35
INSTRUCTION FORMATS AND ENCODINGS
SS:r64 with far pointer from memory 0100 1WXB : 0000 1111 : 1011 0010 : mod
A
qwordreg r/m
LTR – Load Task Register
from register 0100 0R00 : 0000 1111 : 0000 0000 : 11 011
reg
from memory 0100 00XB : 0000 1111 : 0000 0000 : mod
011 r/m
MOV – Move Data
register1 to register2 0100 0R0B : 1000 100w : 11 reg1 reg2
qwordregister1 to qwordregister2 0100 1R0B 1000 1001 : 11 qwordeg1
qwordreg2
register2 to register1 0100 0R0B : 1000 101w : 11 reg1 reg2
qwordregister2 to qwordregister1 0100 1R0B 1000 1011 : 11 qwordreg1
qwordreg2
memory to reg 0100 0RXB : 1000 101w : mod reg r/m
memory64 to qwordregister 0100 1RXB 1000 1011 : mod qwordreg r/m
reg to memory 0100 0RXB : 1000 100w : mod reg r/m
qwordregister to memory64 0100 1RXB 1000 1001 : mod qwordreg r/m
immediate to register 0100 000B : 1100 011w : 11 000 reg : imm
immediate32 to qwordregister (zero extend) 0100 100B 1100 0111 : 11 000 qwordreg :
imm32
immediate to register (alternate encoding) 0100 000B : 1011 w reg : imm
immediate64 to qwordregister (alternate
encoding)
0100 100B 1011 1000 reg : imm64
immediate to memory 0100 00XB : 1100 011w : mod 000 r/m : imm
immediate32 to memory64 (zero extend) 0100 10XB 1100 0111 : mod 000 r/m : imm32
memory to AL, AX, or EAX 0100 0000 : 1010 000w : displacement
memory64 to RAX 0100 1000 1010 0001 : displacement64
AL, AX, or EAX to memory 0100 0000 : 1010 001w : displacement
RAX to memory64 0100 1000 1010 0011 : displacement64
MOV – Move to/from Control Registers
CR0-CR4 from register 0100 0R0B : 0000 1111 : 0010 0010 : 11 eee
reg (eee = CR#)
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding