Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-294 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
SFENCE—Store Fence
Description
Performs a serializing operation on all store-to-memory instructions that were issued
prior the SFENCE instruction. This serializing operation guarantees that every store
instruction that precedes in program order the SFENCE instruction is globally visible
before any store instruction that follows the SFENCE instruction is globally visible.
The SFENCE instruction is ordered with respect store instructions, other SFENCE
instructions, any MFENCE instructions, and any serializing instructions (such as the
CPUID instruction). It is not ordered with respect to load instructions or the LFENCE
instruction.
Weakly ordered memory types can be used to achieve higher processor performance
through such techniques as out-of-order issue, write-combining, and write-
collapsing. The degree to which a consumer of data recognizes or knows that the
data is weakly ordered varies among applications and may be unknown to the
producer of this data. The SFENCE instruction provides a performance-efficient way
of insuring store ordering between routines that produce weakly-ordered results and
routines that consume this data.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
Wait_On_Following_Stores_Until(preceding_stores_globally_visible);
Intel C/C++ Compiler Intrinsic Equivalent
void_mm_sfence(void)
Exceptions (All Operating Modes)
None.
Opcode Instruction
64-Bit
Mode
Compat
/Leg Mode Description
0F AE /7 SFENCE Valid Valid Serializes store operations.