Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-152 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PSHUFD—Shuffle Packed Doublewords
Description
Copies doublewords from source operand (second operand) and inserts them in the
destination operand (first operand) at the locations selected with the order operand
(third operand). Figure 4-7 shows the operation of the PSHUFD instruction and the
encoding of the order operand. Each 2-bit field in the order operand selects the
contents of one doubleword location in the destination operand. For example, bits 0
and 1 of the order operand select the contents of doubleword 0 of the destination
operand. The encoding of bits 0 and 1 of the order operand (see the field encoding in
Figure 4-7) determines which doubleword from the source operand will be copied to
doubleword 0 of the destination operand.
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register. The order operand is an 8-bit immediate. Note
that this instruction permits a doubleword in the source operand to be copied to more
than one doubleword location in the destination operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
66 0F 70 /r ib PSHUFD xmm1,
xmm2/m128, imm8
Valid Valid Shuffle the doublewords
in xmm2/m128 based on
the encoding in imm8 and
store the result in xmm1.
Figure 4-7. PSHUFD Instruction Operation
X3 X2 X1 X0
SRC
DEST
Y3 Y2 Y1 Y0
ORDER
00B - X0
01B - X1
10B - X2
11B - X3
Encoding
of Fields in
ORDER
01234567
Operand