Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-378 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point
Values and Set EFLAGS
Description
Performs and unordered compare of the single-precision floating-point values in the
low doublewords of the source operand 1 (first operand) and the source operand 2
(second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according
to the result (unordered, greater than, less than, or equal). In The OF, SF and AF
flags in the EFLAGS register are set to 0. The unordered result is returned if either
source operand is a NaN (QNaN or SNaN).
Source operand 1 is an XMM register; source operand 2 can be an XMM register or a
32 bit memory location.
The UCOMISS instruction differs from the COMISS instruction in that it signals a
SIMD floating-point invalid operation exception (#I) only when a source operand is
an SNaN. The COMISS instruction signals an invalid operation exception if a source
operand is either a QNaN or an SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is
generated.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
RESULT ← UnorderedCompare(SRC1[31:0] <> SRC2[31:0]) {
(* Set EFLAGS *)
CASE (RESULT) OF
UNORDERED: ZF,PF,CF ← 111;
GREATER_THAN: ZF,PF,CF ← 000;
LESS_THAN: ZF,PF,CF ← 001;
EQUAL: ZF,PF,CF ← 100;
ESAC;
OF,AF,SF ← 0;
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F 2E /r UCOMISS xmm1,
xmm2/m32
Valid Valid Compare lower single-precision
floating-point value in xmm1 register
with lower single-precision floating-
point value in xmm2/mem and set the
status flags accordingly.