Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-91
INSTRUCTION FORMATS AND ENCODINGS
mem to mmreg 0000 1111:0011 1000: 0000 0100: mod mmreg r/m
xmmreg to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0100:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0100: mod xmmreg r/m
PMULHRSW—Packed
Multiply HIgn with Round
and Scale
mmreg to mmreg 0000 1111:0011 1000: 0000 1011:11 mmreg1 mmreg2
mem to mmreg 0000 1111:0011 1000: 0000 1011: mod mmreg r/m
xmmreg to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1011:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1011: mod xmmreg r/m
PSHUFB—Packed Shuffle
Bytes
mmreg to mmreg 0000 1111:0011 1000: 0000 0000:11 mmreg1 mmreg2
mem to mmreg 0000 1111:0011 1000: 0000 0000: mod mmreg r/m
xmmreg to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0000:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 0000: mod xmmreg r/m
PSIGNB—Packed Sign
Bytes
mmreg to mmreg 0000 1111:0011 1000: 0000 1000:11 mmreg1 mmreg2
mem to mmreg 0000 1111:0011 1000: 0000 1000: mod mmreg r/m
xmmreg to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1000:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1000: mod xmmreg r/m
PSIGND—Packed Sign
Double Words
mmreg to mmreg 0000 1111:0011 1000: 0000 1010:11 mmreg1 mmreg2
mem to mmreg 0000 1111:0011 1000: 0000 1010: mod mmreg r/m
xmmreg to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1010:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1010: mod xmmreg r/m
Table B-31. Formats and Encodings for SSSE3 Instructions (Contd.)
Instruction and Format Encoding