Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B INDEX-1
INDEX FOR VOLUMES 2A & 2B
Numerics
64-bit mode
control and debug registers, 2-15
default operand size, 2-15
direct memory-offset MOVs, 2-14
general purpose encodings, B-24
immediates, 2-14
introduction, 2-9
machine instructions, B-1
reg (reg) field, B-4
REX prefixes, 2-9, B-2
RIP-relative addressing, 2-14
SIMD encodings, B-54
special instruction encodings, B-92
summary table notation, 3-7
A
AAA instruction, 3-19
AAD instruction, 3-21
AAM instruction, 3-23
AAS instruction, 3-25
Access rights, segment descriptor, 3-513
ADC instruction, 3-27, 3-541
ADD instruction, 3-19, 3-30, 3-256, 3-541
ADDPD instruction, 3-33
ADDPS instruction, 3-36
Addressing methods
RIP-relative, 2-14
Addressing, segments, 1-6
ADDSD instruction, 3-39
ADDSS instruction, 3-42
ADDSUBPD instruction, 3-45
ADDSUBPS instruction, 3-48
AND instruction, 3-52, 3-541
ANDNPD instruction, 3-59
ANDNPS instruction, 3-61
ANDPD instruction, 3-55
ANDPS instruction, 3-57
Arctangent, x87 FPU operation, 3-354
ARPL instruction, 3-63
B
B (default stack size) flag, segment descriptor, 4-213
Base (operand addressing), 2-4
BCD integers
packed, 3-256, 3-258, 3-292, 3-294
unpacked, 3-19, 3-21, 3-23, 3-25
Binary numbers, 1-5
Bit order, 1-3
BOUND instruction, 3-65
BOUND range exceeded exception (#BR), 3-65
Branch hints, 2-2
Brand information, 3-180
processor brand index, 3-183
processor brand string, 3-181
BSF instruction, 3-68
BSR instruction, 3-70
BSWAP instruction, 3-72
BT instruction, 3-74
BTC instruction, 3-77, 3-541
BTR instruction, 3-80, 3-541
BTS instruction, 3-83, 3-541
Byte order, 1-3
C
Cache and TLB information, 3-176
Caches, invalidating (flushing), 3-480, 4-399
CALL instruction, 3-86
CBW instruction, 3-104
CDQ instruction, 3-254
CDQE instruction, 3-104
CF (carry) flag, EFLAGS register, 3-30, 3-74, 3-77,
3-80, 3-83, 3-105, 3-114, 3-260, 3-453,
3-459, 3-681, 4-229, 4-283, 4-298,
4-301, 4-330, 4-344
CLC instruction, 3-105
CLD instruction, 3-106
CLFLUSH instruction, 3-107
CPUID flag, 3-175
CLI instruction, 3-109
CLTS instruction, 3-112
CMC instruction, 3-114
CMOVcc flag, 3-175
CMOVcc instructions, 3-115
CPUID flag, 3-175
CMP instruction, 3-122
CMPPD instruction, 3-125
CMPPS instruction, 3-130
CMPS instruction, 3-134, 4-250
CMPSB instruction, 3-134
CMPSD instruction, 3-134, 3-140
CMPSQ instruction, 3-134
CMPSS instruction, 3-144
CMPSW instruction, 3-134
CMPXCHG instruction, 3-148, 3-541
CMPXCHG16B instruction, 3-151
CPUID bit, 3-172
CMPXCHG8B instruction, 3-151
CPUID flag, 3-174
COMISD instruction, 3-154
COMISS instruction, 3-157
Compatibility mode
introduction, 2-9
see 64-bit mode
summary table notation, 3-7