Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-86 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
B.9 SSE3 FORMATS AND ENCODINGS TABLE
The tables in this section provide SSE3 formats and encodings. Some SSE3 instruc-
tions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte opcode.
These prefixes are included in the tables.
When in IA-32e mode, use of the REX.R prefix permits instructions that use general
purpose and XMM registers to access additional registers. Some instructions require
the REX.W prefix to promote the instruction to 64-bit operation. Instructions that
require the REX.W prefix are listed (with their opcodes) in Section B.11.
Table B-28. Formats and Encodings of SSE3 Floating-Point Instructions
Instruction and Format Encoding
ADDSUBPD—Add /Sub packed DP FP
numbers from XMM2/Mem to XMM1
xmmreg2 to xmmreg1 01100110:00001111:11010000:11 xmmreg1
xmmreg2
mem to xmmreg 01100110:00001111:11010000: mod xmmreg
r/m
ADDSUBPS—Add /Sub packed SP FP
numbers from XMM2/Mem to XMM1
xmmreg2 to xmmreg1 11110010:00001111:11010000:11 xmmreg1
xmmreg2
mem to xmmreg 11110010:00001111:11010000: mod xmmreg
r/m
HADDPD—Add horizontally packed DP FP
numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1 01100110:00001111:01111100:11 xmmreg1
xmmreg2
mem to xmmreg 01100110:00001111:01111100: mod xmmreg
r/m
HADDPS—Add horizontally packed SP FP
numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1 11110010:00001111:01111100:11 xmmreg1
xmmreg2
mem to xmmreg 11110010:00001111:01111100: mod xmmreg
r/m
HSUBPD—Sub horizontally packed DP FP
numbers XMM2/Mem to XMM1
xmmreg2 to xmmreg1 01100110:00001111:01111101:11 xmmreg1
xmmreg2