Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-33
INSTRUCTION FORMATS AND ENCODINGS
LAR – Load Access Rights Byte
from register 0100 0R0B : 0000 1111 : 0000 0010 : 11
reg1 reg2
from dwordregister to qwordregister, masked
by 00FxFF00H
0100 WR0B : 0000 1111 : 0000 0010 : 11
qwordreg1 dwordreg2
from memory 0100 0RXB : 0000 1111 : 0000 0010 : mod
reg r/m
from memory32 to qwordregister, masked by
00FxFF00H
0100 WRXB 0000 1111 : 0000 0010 : mod
r/m
LEA – Load Effective Address
in wordregister/dwordregister 0100 0RXB : 1000 1101 : mod
A
reg r/m
in qwordregister 0100 1RXB : 1000 1101 : mod
A
qwordreg r/m
LEAVE – High Level Procedure Exit 1100 1001
LFS – Load Pointer to FS
FS:r16/r32 with far pointer from memory 0100 0RXB : 0000 1111 : 1011 0100 : mod
A
reg r/m
FS:r64 with far pointer from memory 0100 1RXB : 0000 1111 : 1011 0100 : mod
A
qwordreg r/m
LGDT – Load Global Descriptor Table Register 0100 10XB : 0000 1111 : 0000 0001 : mod
A
010 r/m
LGS – Load Pointer to GS
GS:r16/r32 with far pointer from memory 0100 0RXB : 0000 1111 : 1011 0101 : mod
A
reg r/m
GS:r64 with far pointer from memory 0100 1RXB : 0000 1111 : 1011 0101 : mod
A
qwordreg r/m
LIDT – Load Interrupt Descriptor Table
Register
0100 10XB : 0000 1111 : 0000 0001 : mod
A
011 r/m
LLDT – Load Local Descriptor Table Register
LDTR from register 0100 000B : 0000 1111 : 0000 0000 : 11 010
reg
LDTR from memory 0100 00XB :0000 1111 : 0000 0000 : mod
010 r/m
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding