Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-23

INSTRUCTION FORMATS AND ENCODINGS

AX or EAX with reg 1001 0 reg

memory with reg 1000 011w : mod reg r/m

XLAT/XLATB – Table Look-up Translation 1101 0111

XOR – Logical Exclusive OR

register1 to register2 0011 000w : 11 reg1 reg2

register2 to register1 0011 001w : 11 reg1 reg2

memory to register 0011 001w : mod reg r/m

immediate to register 1000 00sw : 11 110 reg : immediate data

immediate to AL, AX, or EAX 0011 010w : immediate data

immediate to memory 1000 00sw : mod 110 r/m : immediate data

Prefix Bytes

address size 0110 0111

LOCK 1111 0000

operand size 0110 0110

CS segment override 0010 1110

DS segment override 0011 1110

ES segment override 0010 0110

FS segment override 0110 0100

GS segment override 0110 0101

SS segment override 0011 0110

NOTES:

1. The multi-byte NOP instruction does not alter the content of the register and will not issue a

memory

operation.

Table B-13. General Purpose Instruction Formats and Encodings

for Non-64-Bit Modes (Contd.)

Instruction and Format Encoding