Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-346 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
SUBPD—Subtract Packed Double-Precision Floating-Point Values
Description
Performs a SIMD subtract of the two packed double-precision floating-point values in
the source operand (second operand) from the two packed double-precision floating-
point values in the destination operand (first operand), and stores the packed
double-precision floating-point results in the destination operand. The source
operand can be an XMM register or a 128-bit memory location. The destination
operand is an XMM register. See Figure 11-3 in the Intel
®
64 and IA-32 Architectures
Software Developer’s Manual, Volume 1, for an illustration of a SIMD double-preci-
sion floating-point operation.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
DEST[63:0] ← DEST[63:0] − SRC[63:0];
DEST[127:64] ← DEST[127:64]
− SRC[127:64];
Intel C/C++ Compiler Intrinsic Equivalent
SUBPD __m128d _mm_sub_pd (m128d a, m128d b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
If a memory operand is not aligned on a 16-byte boundary,
regardless of segment.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
66 0F 5C
/r
SUBPD xmm1,
xmm2/m128
Valid Valid Subtract packed double-precision
floating-point values in
xmm2/m128 from xmm1.