Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-184 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
THEN
DEST[64:0] ← 0000000000000000H
ELSE
DEST ← ZeroExtend(DEST
>> COUNT);
FI;
PSRLW instruction with 128-bit operand:
COUNT ← COUNT_SOURCE[63:0];
IF (COUNT > 15)
THEN
DEST[128:0] ← 00000000000000000000000000000000H
ELSE
DEST[15:0] ← ZeroExtend(DEST[15:0]
>> COUNT);
(* Repeat shift operation for 2nd through 7th words *)
DEST[127:112] ← ZeroExtend(DEST[127:112]
>> COUNT);
FI;
PSRLD instruction with 128-bit operand:
COUNT ← COUNT_SOURCE[63:0];
IF (COUNT > 31)
THEN
DEST[128:0] ← 00000000000000000000000000000000H
ELSE
DEST[31:0] ← ZeroExtend(DEST[31:0]
>> COUNT);
(* Repeat shift operation for 2nd and 3rd doublewords *)
DEST[127:96] ← ZeroExtend(DEST[127:96]
>> COUNT);
FI;
PSRLQ instruction with 128-bit operand:
COUNT ← COUNT_SOURCE[63:0];
IF (COUNT > 15)
THEN
DEST[128:0] ← 00000000000000000000000000000000H
ELSE
DEST[63:0] ← ZeroExtend(DEST[63:0]
>> COUNT);
DEST[127:64] ← ZeroExtend(DEST[127:64]
>> COUNT);
FI;
Intel C/C++ Compiler Intrinsic Equivalents
PSRLW __m64 _mm_srli_pi16(__m64 m, int count)
PSRLW __m64 _mm_srl_pi16 (__m64 m, __m64 count)
PSRLW __m128i _mm_srli_epi16 (__m128i m, int count)
PSRLW __m128i _mm_srl_epi16 (__m128i m, __m128i count)