Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-110 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PMULHRSW — Packed Multiply High with Round and Scale
Description
PMULHRSW multiplies vertically each signed 16-bit integer from the destination
operand (first operand) with the corresponding signed 16-bit integer of the source
operand (second operand), producing intermediate, signed 32-bit integers. Each
intermediate 32-bit integer is truncated to the 18 most significant bits. Rounding is
always performed by adding 1 to the least significant bit of the 18-bit intermediate
result. The final result is obtained by selecting the 16 bits immediately to the right of
the most significant bit of each 18-bit intermediate result and packed to the destina-
tion operand. Both operands can be MMX register or XMM registers. When the source
operand is a 128-bit memory operand, the operand must be aligned on a 16-byte
boundary or a general-protection exception (#GP) will be generated.
In 64-bit mode, use the REX prefix to access additional registers.
Operation
PMULHRSW wi64-bit operands:
temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
temp1[31:0] = INT32 ((DEST[31:15] * SRC[31:15]) >>14) + 1;
temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >> 14) + 1;
temp3[31:0] = INT32 ((DEST[63:48] * SRc[63:48]) >> 14) + 1;
DEST[15:0] = temp0[16:1];
DEST[31:15] = temp1[16:1];
DEST[47:32] = temp2[16:1];
DEST[63:48] = temp3[16:1];
PMULHRSW with 128-bit operand:
temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
temp1[31:0] = INT32 ((DEST[31:15] * SRC[31:15]) >>14) + 1;
temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >>14) + 1;
temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) >>14) + 1;
temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) >>14) + 1;
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F 38 0B /r PMULHRSW
mm1,
mm2/m64
Valid Valid Multiply 16-bit signed
words, scale and round
signed doublewords, pack
high 16 bits to MM1.
66 0F 38 0B /r PMULHRSW
xmm1,
xmm2/m128
Valid Valid Multiply 16-bit signed
words, scale and round
signed doublewords, pack
high 16 bits to XMM1.