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Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

ManualsBrandsIntel ManualsOtherIntel Pentium 4 Processor 1.60 GHz, 512K Cache, 400 MHz FSB
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B-84 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
PSUBUS—Subtract Unsigned With
Saturation
xmmreg2 from xmmreg1 0000 1111:1101 10gg: 11 xmmreg1 xmmreg2
memory from xmmreg 0000 1111:1101 10gg: mod xmmreg r/m
PUNPCKH—Unpack High Data To
Next Larger Type
xmmreg to xmmreg 0110 0110:0000 1111:0110 10gg:11 xmmreg1
Xmmreg2
mem to xmmreg 0110 0110:0000 1111:0110 10gg: mod xmmreg r/m
PUNPCKHQDQ—Unpack High Data
xmmreg to xmmreg 0110 0110:0000 1111:0110 1101:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0110 1101: mod xmmreg r/m
PUNPCKL—Unpack Low Data To Next
Larger Type
xmmreg to xmmreg 0110 0110:0000 1111:0110 00gg:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0110 00gg: mod xmmreg r/m
PUNPCKLQDQ—Unpack Low Data
xmmreg to xmmreg 0110 0110:0000 1111:0110 1100:11 xmmreg1
xmmreg2
mem to xmmreg 0110 0110:0000 1111:0110 1100: mod xmmreg r/m
PXOR—Bitwise Xor
xmmreg2 to xmmreg1 0110 0110:0000 1111:1110 1111: 11 xmmreg1
xmmreg2
memory to xmmreg 0110 0110:0000 1111:1110 1111: mod xmmreg r/m
Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.)
Instruction and Format Encoding