Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-60 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
B.7 SSE INSTRUCTION FORMATS AND ENCODINGS
The SSE instructions use the ModR/M format and are preceded by the 0FH prefix
byte. In general, operations are not duplicated to provide two directions (that is,
separate load and store variants).
The following three tables (Tables B-21, B-22, and B-23) show the formats and
encodings for the SSE SIMD floating-point, SIMD integer, and cacheability and
memory ordering instructions, respectively. Some SSE instructions require a manda-
tory prefix (66H, F2H, F3H) as part of the two-byte opcode. Mandatory prefixes are
included in the tables.
Table B-21. Formats and Encodings of SSE Floating-Point Instructions
Instruction and Format Encoding
ADDPS—Add Packed Single-Precision
Floating-Point Values
xmmreg to xmmreg 0000 1111:0101 1000:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 1000: mod xmmreg r/m
ADDSS—Add Scalar Single-Precision
Floating-Point Values
xmmreg to xmmreg 1111 0011:0000 1111:01011000:11 xmmreg1
xmmreg2
mem to xmmreg 1111 0011:0000 1111:01011000: mod xmmreg r/m
ANDNPS—Bitwise Logical AND NOT of
Packed Single-Precision Floating-Point
Values
xmmreg to xmmreg 0000 1111:0101 0101:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 0101: mod xmmreg r/m
ANDPS—Bitwise Logical AND of Packed
Single-Precision Floating-Point Values
xmmreg to xmmreg 0000 1111:0101 0100:11 xmmreg1 xmmreg2
mem to xmmreg 0000 1111:0101 0100: mod xmmreg r/m
CMPPS—Compare Packed Single-
Precision Floating-Point Values
xmmreg to xmmreg, imm8 0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8
mem to xmmreg, imm8 0000 1111:1100 0010: mod xmmreg r/m: imm8
CMPSS—Compare Scalar Single-
Precision Floating-Point Values
xmmreg to xmmreg, imm8 1111 0011:0000 1111:1100 0010:11 xmmreg1
xmmreg2: imm8