Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B B-39
INSTRUCTION FORMATS AND ENCODINGS
immediate8 to memory8 0100 00XB 1000 0000 : mod 001 r/m : imm8
immediate32 to memory64 0100 00XB 1000 0001 : mod 001 r/m : imm32
immediate8 to memory64 0100 00XB 1000 0011 : mod 001 r/m : imm8
OUT – Output to Port
fixed port 1110 011w : port number
variable port 1110 111w
OUTS – Output to DX Port
output to DX Port 0110 111w
POP – Pop a Value from the Stack
wordregister 0101 0101 : 0100 000B : 1000 1111 : 11 000
reg16
qwordregister 0100 W00B
S
: 1000 1111 : 11 000 reg64
wordregister (alternate encoding) 0101 0101 : 0100 000B : 0101 1 reg16
qwordregister (alternate encoding) 0100 W00B : 0101 1 reg64
memory64 0100 W0XB
S
: 1000 1111 : mod 000 r/m
memory16 0101 0101 : 0100 00XB 1000 1111 : mod
000 r/m
POP – Pop a Segment Register from the Stack
(Note: CS cannot be sreg2 in this usage.)
segment register FS, GS 0000 1111: 10 sreg3 001
POPF/POPFQ – Pop Stack into FLAGS/RFLAGS
Register
pop stack to FLAGS register 0101 0101 : 1001 1101
pop Stack to RFLAGS register 0100 1000 1001 1101
PUSH – Push Operand onto the Stack
wordregister 0101 0101 : 0100 000B : 1111 1111 : 11 110
reg16
qwordregister 0100 W00B
S
: 1111 1111 : 11 110 reg64
wordregister (alternate encoding) 0101 0101 : 0100 000B : 0101 0 reg16
qwordregister (alternate encoding) 0100 W00B
S
: 0101 0 reg64
memory16 0101 0101 : 0100 000B : 1111 1111 : mod
110 r/m
Table B-15. General Purpose Instruction Formats and Encodings
for 64-Bit Mode (Contd.)
Instruction and Format Encoding