Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-242 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
The Pentium 4 and Intel Xeon processors also support “fast” (32-bit) and “slow”
(40-bit) reads on the first 18 performance counters. Selected this option using
ECX[bit 31]. If bit 31 is set, RDPMC reads only the low 32 bits of the selected perfor-
mance counter. If bit 31 is clear, all 40 bits are read. A 32-bit result is returned in EAX
and EDX is set to 0. A 32-bit read executes faster on Pentium 4 processors and Intel
Xeon processors than a full 40-bit read.
On 64-bit Intel Xeon processors with L3, performance counters with indices 18-25
are 32-bit counters. EDX is cleared after executing RDPMC for these counters.
When in protected or virtual 8086 mode, the performance-monitoring counters
enabled (PCE) flag in register CR4 restricts the use of the RDPMC instruction as
follows. When the PCE flag is set, the RDPMC instruction can be executed at any priv-
ilege level; when the flag is clear, the instruction can only be executed at privilege
level 0. (When in real-address mode, the RDPMC instruction is always enabled.)
The performance-monitoring counters can also be read with the RDMSR instruction,
when executing at privilege level 0.
The performance-monitoring counters are event counters that can be programmed
to count events such as the number of instructions decoded, number of interrupts
received, or number of cache loads. Appendix A, “Performance Monitoring Events,” in
the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, lists
the events that can be counted for various processors in the Intel 64 and IA-32
architecture families.
The RDPMC instruction is not a serializing instruction; that is, it does not imply that
all the events caused by the preceding instructions have been completed or that
events caused by subsequent instructions have not begun. If an exact event count is
desired, software must insert a serializing instruction (such as the CPUID instruction)
before and/or after the RDPCM instruction.
In the Pentium 4 and Intel Xeon processors, performing back-to-back fast reads are
not guaranteed to be monotonic. To guarantee monotonicity on back-to-back reads,
a serializing instruction must be placed between the tow RDPMC instructions.
The RDPMC instruction can execute in 16-bit addressing mode or virtual-8086 mode;
however, the full contents of the ECX register are used to select the counter, and the
event count is stored in the full EAX and EDX registers. The RDPMC instruction was
introduced into the IA-32 Architecture in the Pentium Pro processor and the Pentium
processor with MMX technology. The earlier Pentium processors have performance-
monitoring counters, but they must be read with the RDMSR instruction.
In 64-bit mode, RDPMC behavior is unchanged from 32-bit mode. The upper 32 bits
of RAX and RDX are cleared.
Operation
(* Intel Core 2 Duo processor family and Intel Xeon processor 5100 series*)
IF (ECX
= 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
THEN IF (ECX[31]
= 1)