Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-121
INSTRUCTION SET REFERENCE, N-Z
DEST[15:0] ← TEMP0[15:0];
DEST[31:16] ← TEMP1[15:0];
DEST[47:32] ← TEMP2[15:0];
DEST[63:48] ← TEMP3[15:0];
PMULLW instruction with 64-bit operands:
TEMP0[31:0] ← DEST[15:0]
∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] ← DEST[31:16]
∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32]
∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48]
∗ SRC[63:48];
TEMP4[31:0] ← DEST[79:64]
∗ SRC[79:64];
TEMP5[31:0] ← DEST[95:80]
∗ SRC[95:80];
TEMP6[31:0] ← DEST[111:96]
∗ SRC[111:96];
TEMP7[31:0] ← DEST[127:112]
∗ SRC[127:112];
DEST[15:0] ← TEMP0[15:0];
DEST[31:16] ← TEMP1[15:0];
DEST[47:32] ← TEMP2[15:0];
DEST[63:48] ← TEMP3[15:0];
DEST[79:64] ← TEMP4[15:0];
DEST[95:80] ← TEMP5[15:0];
DEST[111:96] ← TEMP6[15:0];
DEST[127:112] ← TEMP7[15:0];
Intel C/C++ Compiler Intrinsic Equivalent
PMULLW __m64 _mm_mullo_pi16(__m64 m1, __m64 m2)
PMULLW __m128i _mm_mullo_epi16 ( __m128i a, __m128i b)
Flags Affected
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
(128-bit operations only) If a memory operand is not aligned on
a 16-byte boundary, regardless of segment.
#SS(0) If a memory operand effective address is outside the SS
segment limit.